On Efficiency of Transport Triggered Architectures in DSP Applications
نویسندگان
چکیده
The trend in programmable architectures for digital signal processing (DSP) is to move towards high-level language programming, which sets high requirements for compilers to efficiently exploit the instruction level parallelism in modern processors. In this paper, efficiency of transport triggered architectures (TTA) in DSP applications is discussed. The efficiency of a high-level compiler on a TTA is compared to commercial very long instruction word DSP architecture. The effect of different coding styles in high-level language code is evaluated with a DSP benchmark, fast Fourier transform. Key-Words: transport triggered architecture, customizable processor architecture, digital signal processing, fast fourier transform, coding style, performance evaluation
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